AMD announces three-core desktop CPU

AMD has yet to name the date when it will ship the desktop ‘Phenom' processor based on its the Barcelona quad-core platform, but it today announced a new member of the family: a three-core CPU that will slide in between the quad-core Phenom X4 superslab and the dual-core Phenom X2.

Three-way bet: the triple-core Phenom x3 is a Phenom x4 quad-core with one (non-working) core disabled

Predictably christened the Phenom X3, it's actually a quad-core CPU on which one of the cores isn't working and is thus disabled. This novel approach isn't new to the tech industry: it's long been rumoured (but never confirmed by Intel) that the single-engine Core Solo processors were dual-core silicon on which one core had blown a fuse.

You can go as far back as the days of 5.25 inch floppy drives, when 720Kb disks which failed testing but could be formatted at a lower capacity were re-badged and sold as 360Kb disks.

For AMD, the X3 offers a smart way to maximise the output of its Barcelona plants. The percentage of working processors which can be obtained from a single silicon wafer, known as "yield", is always a factor in CPU production. The more complex the process, the potentially lower the yield. And the complexity of the Barcelona blueprint, which bakes four processor cores onto a single piece of silicon (compared to Intel's simpler quad-core strategy of bolting together a pair of dual-core CPUs), has hamstrung AMD for much of this year.

In an interview with The San Jose Mercury News last month, AMD boss Hector Ruiz admitted that "every time we ran into a (problem) it created a six-week-or-so hole in the schedule as we went back and fixed it. We hoped we wouldn't get many of those, but in the Barcelona case, we got more than we thought. By the time we got through fixing them all, we were six months-plus later from where we originally wanted to be."

While those glitches may or may not have to do with yields, no CPU production process is ever 100% efficient (Intel is believed to hit over 90%, although numbers are never talked about). So finding a way to sell chips which fail testing due to a non-working core, and thus would usually be tossed into the trash can, is simply good business.

It's also a smart move in what is shaping up to be a very competitive market. Intel's decision to pair two dual-cores into a single ‘dual die' package, rather than design a quad-core processor from the ground up, enabled Intel to bring quad core processors to the market in November last year, giving them a full year's head start over AMD and also leveraging the costs and efficiencies of its existing dual-core lines. Since then, Intel has slashed prices on many of its quad-core processors - in one instance bringing its entry-level Core2 Quad Processor (the 2.4GHz Q6600, with an 8Mb L2 cache and 1066 MHz FSB) down to the same US$266 price as its fastest non-Extreme Core 2 Duo desktop chip (the 3GHz E6850 with 4MB of L2 cache)... a clear sign that Intel is extremely keen to establish quad-core dominance before AMD gets a foothold.

It's feasible that more price cuts could be on the cards once the Phenom X4 arrives towards the end of this year.
AMD says the X3 won't ship until the first quarter of 2008 - this would partly be to avoid stealing the Phenom X4's thunder and eating into its sales, as well as allowing AMD to collect enough X4 ‘cast-offs' to offer the X3 in decent quantity to PC manufacturers and the direct sales channel.

However, the right pricing could steal sales away from Intel's own dual-core offerings, and not just on the basis of having one more core. The rest of the Phenom X4's Barcelona architecture will be intact, including a 2MB bucket of Level 3 cache that's shared among all cores in addition to the Level 1 and Level 2 memory allocated to each core.

How to build your own triple core CPU: grab a red pen and scribble out one of these four cores from the Barcelona platform (APCmag.com is not liable for damage to your monitor)

"We still have L1 and a large (512Kb) L2 caches that are independent for each core, so even if one core is running a command that's going to eat up all the Level 3 cache the other cores can still remain active and access and process data" explains John Fruehe, AMD's Worldwide Business Development Manager.

"When you have only two levels of cache and the L2 is shared between a pair of dual cores, if one of the core pairs needs to take up the entire cache it effectively blocks out the other core and they're left with only a very small L1."

The L3 cache also makes for a faster and more efficient memory transport, says Fruehe. "In a multicore scenario the cores often need access to the same data, especially if you have cores sharing a task, such as in a multithreaded application. If one of the cores needs data that's already been cached by the second core, it doesn't need to travel down trough the front side bus and the memory controller. Core A just grabs it straight from core B."

Fruehe also cites the benefits of Barcelona's design for virtualisation, which is becoming increasingly appealing to desktop users running multiple operating systems and even bespoke gaming environments which have been stripped back for optimum performance and hardware compatibility.

AMD already boasts an advantage in virtualisation with its integrated memory controller creating a fast pipeline between the processor and system memory. In Phenom the controller will support DDR2, but it's more significant that Barcelona will allow "direct communications between the virtual machine and memory without having to go through the hypervisor" touts Fruehe.

"Virtualisation is highly memory intensive, but because the VM now has direct access to memory this way there's less swapping and less overhead. We're seeing a 79% increase in virtualisation performance between our own dual-core and quad-core processors, even though the dual cores had significantly faster clock speeds".